[ Avaa Bypassed ]

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  <comment>Verilog source code</comment>
  <comment xml:lang="bg">Изходен код — Verilog</comment>
  <comment xml:lang="ca">codi font en Verilog</comment>
  <comment xml:lang="cs">zdrojový kód Verilog</comment>
  <comment xml:lang="da">Verilog-kildekode</comment>
  <comment xml:lang="de">Verilog-Quelltext</comment>
  <comment xml:lang="el">Πηγαίος κώδικας Verilog</comment>
  <comment xml:lang="en_GB">Verilog source code</comment>
  <comment xml:lang="eo">Verilog-fontkodo</comment>
  <comment xml:lang="es">código fuente en Verilog</comment>
  <comment xml:lang="eu">Verilog iturburu-kodea</comment>
  <comment xml:lang="fi">Verilog-lähdekoodi</comment>
  <comment xml:lang="fr">code source Verilog</comment>
  <comment xml:lang="gl">código fonte en Verilog</comment>
  <comment xml:lang="he">קוד מקור של </comment>
  <comment xml:lang="hr">Verilog izvorni kod</comment>
  <comment xml:lang="hu">Verilog-forráskód</comment>
  <comment xml:lang="ia">Codice-fonte Verilog</comment>
  <comment xml:lang="id">Kode sumber Verilog</comment>
  <comment xml:lang="it">Codice sorgente Verilog</comment>
  <comment xml:lang="ja">Verilog ソースコード</comment>
  <comment xml:lang="kk">Verilog бастапқы коды</comment>
  <comment xml:lang="ko">Verilog 소스 코드</comment>
  <comment xml:lang="lv">Verilog pirmkods</comment>
  <comment xml:lang="nl">Verilog broncode</comment>
  <comment xml:lang="oc">còde font Verilog</comment>
  <comment xml:lang="pl">Kod źródłowy Verilog</comment>
  <comment xml:lang="pt">código origem Verilog</comment>
  <comment xml:lang="pt_BR">Código-fonte Verilog</comment>
  <comment xml:lang="ru">исходный код Verilog</comment>
  <comment xml:lang="sk">Zdrojový kód Verilog</comment>
  <comment xml:lang="sl">Datoteka izvorne kode Verilog</comment>
  <comment xml:lang="sr">изворни код Верилога</comment>
  <comment xml:lang="sv">Verilog-källkod</comment>
  <comment xml:lang="tr">Verilog kaynak kodu</comment>
  <comment xml:lang="uk">вихідний код мовою Verilog</comment>
  <comment xml:lang="zh_CN">Verilog 源代码</comment>
  <comment xml:lang="zh_TW">Verilog 源碼</comment>
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